In integrated circuit fabrication, millions or more of electronic components are integrally formed over a wafer. In some cases, a few of the electronic components in the wafer may fail, and thus cannot function normally. In conventional integrated circuit fabrication, the electronic components cannot be electrically tested until back end of line (BEOL) routing is accomplished. This results in high waste due to having to abort the entire wafer or chip since additional processes are performed before errors are detected.
This Discussion of the Background section is for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes a prior art to the present disclosure, and no part of this section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.